1. Technical Field
The present invention relates, generally, to a timing recovery circuit for use in telecommunications applications and, more particularly, to an improved finite impulse response interpolation filter for use in adjusting the sampling clock.
2. Background of the Invention
Data transmission systems, for example, telecommunications systems, are capable of transmitting large volumes of data at very high speeds. In recovering transmitted data, it is often necessary to compensate for the effects of the channel. For example, when data is sent through the Public Switched Telephone Network (PSTN), the analog loop tends to impart jitter, distortion, and other channel effects to the data. Accordingly, upon receiving and recovering the data, it is important to ensure that the data is sampled synchronously with the clock which controlled the data transmission. Efficient and accurate timing recovery is essential to preserving the integrity of transmitted data.
In a T1/E1 Receive Line Interface Unit (RLIU), timing recovery and input data jitter tolerance requirements are laid out in ATandT publication number 62411, the entire contents of which are hereby incorporated by reference. Thus, companies desiring to provide data communications chip sets, and particularly transceiver chip sets, for use in connection with the PSTN generally strive to comply with the requirements set forth in ATandT Pub 62411.
Many different techniques have been employed to compensate for jitter imposed on a data stream by the communication channel. One such technique is known as the Tiernan Communications Design, wherein a zero-crossing algorithm running at two times symbol rate is employed. This technique is desirable because it focuses on the zero-crossing point, which is generally quite easy to detect at the receiver circuit. However, the signal to noise ratio near the zero-crossing is quite low, making this technique ill-suited for many applications.
Another prior art technique for timing recovery is known as early-late detection, and is typically employed in a four times sampling mode. In this technique, the difference between an early and a late sample around the symbol are taken, and this information is used to adjust the sampling clock. Although this technique is theoretically attractive, the four times sampling rate computational requirement is difficult to achieve within the power and die size constraints needed to produce competitive products.
A timing recovery technique is thus needed which overcomes the shortcomings of the prior art.
In accordance with a preferred embodiment of the present invention, an xe2x80x9cearlyxe2x80x9d sample value and a xe2x80x9clatexe2x80x9d sample value are calculated from a single sampled data point, and the early and late sample information used to adjust the timing of the sampling clock. In accordance with a particularly preferred embodiment, the early and late sample points are calculated from the sampled data point and zero crossing, eliminating the need to physically retrieve early and late sampled data. This effectively provides 4xc3x97 sampling information in the context of a 2xc3x97 sampling chip set.
In accordance with a further aspect of the present invention, rather than employing a first filter to compute an early sample point and a second filter to compute a late sample point, a single multiplication stage is employed to compute the difference between the early and the late interpolated data points, with the xe2x80x9cdifferencexe2x80x9d being manifested as a predetermined multiplier coefficient within the filter.
In accordance with a further aspect of the present invention, the algorithm of the present invention may be generalized to accommodate virtually any filter order and virtually any number of desired interpolation points, using only a single multiplication stage for any number of desired interpolation points.